Hardware emulation of stochastic p-bits for invertible logic

The common feature of nearly all logic and memory devices is that they make use of stable units to represent 0's and 1's. A completely different paradigm is based on three-terminal stochastic units which could be called "p-bits", where the output is a random telegraphic signal continuously fluctuating between 0 and 1 with a tunable mean. p-bits can be interconnected to receive weighted contributions from others in a network, and these weighted contributions can be chosen to not only solve problems of optimization and inference but also to implement precise Boolean functions in an inverted mode. This inverted operation of Boolean gates is particularly striking: They provide inputs consistent to a given output along with unique outputs to a given set of inputs. The existing demonstrations of accurate invertible logic are intriguing, but will these striking properties observed in computer simulations carry over to hardware implementations? This paper uses individual micro controllers to emulate p-bits, and we present results for a 4-bit ripple carry adder with 48 p-bits and a 4-bit multiplier with 46 p-bits working in inverted mode as a factorizer. Our results constitute a first step towards implementing p-bits with nano devices, like stochastic Magnetic Tunnel Junctions

Weighted p-bits for FPGA implementation of probabilistic circuits

Probabilistic spin logic (PSL) is a recently proposed computing paradigm based on unstable stochastic units called probabilistic bits (p-bits) that can be correlated to form probabilistic circuits (p-circuits). These p-circuits can be used to solve problems of optimization, inference and also to implement precise Boolean functions in an "inverted" mode, where a given Boolean circuit can operate in reverse to find the input combinations that are consistent with a given output. In this paper we present a scalable FPGA implementation of such invertible p-circuits. We implement a "weighted" p-bit that combines stochastic units with localized memory structures. We also present a generalized tile of weighted p-bits to which a large class of problems beyond invertible Boolean logic can be mapped, and how invertibility can be applied to interesting problems such as the NP-complete Subset Sum Problem by solving a small instance of this problem in hardware

The inclusive analysis of ICT ethical issues on healthy society: a global digital divide approach

The Global Digital Division remains as a rising focus that has to be brought into the notice of the United Nations UN. It is about the vast disparity in exposure to the existing digital knowledge by ICT information and communication technologies amongst developed and developing nations. The work outlined here seeks to acknowledge the effects and provide feedback of an ethical issue on key areas. The study also provides information about the several concrete solutions to this issue in order to ensure the sustainable development of society. In addition, a Digital Effectiveness Framework has been suggested which consist of five phases namely access, exploration, knowledge acquisition, adoption, and innovation and transformation. The study ends with the molds that leads to address the impact of the Global Digital Divide will continue at national level. National surveillance systems must be set to determine the digital opportunity index DOI for each country and track their role as tech giants in the information and communication technology environment

Impact of IoT on Manufacturing Industry 4.0: A New Triangular Systematic Review

The Internet of Things (IoT) has realised the fourth industrial revolution concept; however, its applications in the manufacturing industry are relatively sparse and primarily investigated without contextual peculiarities. Our research undertakes an intricate critical review to investigate significant aspects of IoT applications in the manufacturing Industry 4.0 perspective to address this gap. We adopt a systematic literature review approach by Denyer and Tranfield (2009) to carry out critical analyses that help develop future research domains based on empirical studies. We describe key knowledge gaps in the existing literature and empirical studies by exploring the main contribution categories and finding six critical differences between traditional and manufacturing Industry 4.0 and 10 enablers and 11 challenges of IoT applications. Finally, an agenda for future research is proposed with 11 research domains to focus on the recognised gaps

Hardware Implementation of Autonomous Probabilistic Computers

Conventional digital computers are built using stable deterministic units known as “bits”. These conventional computers have greatly evolved into sophisticated machines, however there are many classes of problems such as optimization, sampling and machine learning that still cannot be addressed efficiently with conventional computing. Quantum computing, which uses q-bits, that are in a delicate superposition of 0 and 1, is expected to perform some of these tasks efficiently. However, decoherence, requirements for cryogenic operation and limited many-body interactions pose significant challenges to scaled quantum computers. Probabilistic computing is another unconventional computing paradigm which introduces the concept of a probabilistic bit or “p-bit”; a robust classical entity fluctuating between 0 and 1 and can be interconnected electrically. The primary contribution of this thesis is the first experimental proof-of-concept demonstration of p-bits built by slight modifications to the magnetoresistive random-access memory (MRAM) operating at room temperature. These p-bits are connected to form a clock-less autonomous probabilistic computer. We first set the stage, by demonstrating a high-level emulation of p-bits which establishes important rules of operation for autonomous p-computers. The experimental demonstration is then followed by a low-level emulation of MRAM based p-bits which will allow further study of device characteristics and parameter variations for proper operation of p-computers. We lastly demonstrate an FPGA based scalable synchronous probabilistic computer which uses almost 450 digital p-bits to demonstrate large p-circuits

Hardware emulation of stochastic p-bits for invertible logic.

The common feature of nearly all logic and memory devices is that they make use of stable units to represent 0's and 1's. A completely different paradigm is based on three-terminal stochastic units which could be called "p-bits", where the output is a random telegraphic signal continuously fluctuating between 0 and 1 with a tunable mean. p-bits can be interconnected to receive weighted contributions from others in a network, and these weighted contributions can be chosen to not only solve problems of optimization and inference but also to implement precise Boolean functions in an inverted mode. This inverted operation of Boolean gates is particularly striking: They provide inputs consistent to a given output along with unique outputs to a given set of inputs. The existing demonstrations of accurate invertible logic are intriguing, but will these striking properties observed in computer simulations carry over to hardware implementations? This paper uses individual micro controllers to emulate p-bits, and we present results for a 4-bit ripple carry adder with 48 p-bits and a 4-bit multiplier with 46 p-bits working in inverted mode as a factorizer. Our results constitute a first step towards implementing p-bits with nano devices, like stochastic Magnetic Tunnel Junctions

Weighted p -Bits for FPGA Implementation of Probabilistic Circuits.

Probabilistic spin logic is a recently proposed computing paradigm based on unstable stochastic units called probabilistic bits ( p -bits) that can be correlated to form probabilistic circuits (p-circuits). These p-circuits can be used to solve the problems of optimization, inference, and implement precise Boolean functions in an "inverted" mode, where a given Boolean circuit can operate in reverse to find the input combinations that are consistent with a given output. In this brief, we present a scalable field-programmable gate array implementation of such invertible p-circuits. We implement a "weighted" p -bit that combines stochastic units with localized memory structures. We also present a generalized tile of weighted p -bits to which a large class of problems beyond invertible Boolean logic can be mapped and how invertibility can be applied to interesting problems such as the NP-complete subset sum problem by solving a small instance of this problem in hardware